Title :
Application of the modified voltage-dividing potentiometer to overlay metrology in a CMOS/bulk process
Author :
Allen, R.A. ; Cresswell, M.W. ; Linholm, L.W. ; Owen, J.C. ; Ellenwood, C.H. ; Hill, T.A. ; Benecke, J.D. ; Volk, S.R. ; Stewart, H.D.
Author_Institution :
Semicond. Electron. Div., Nat. Inst. of Stand. & Technol., Gaithersburg, MD, USA
Abstract :
The measurement of layer-to-layer feature overlay will, in the foreseeable future, continue to be a critical metrological requirement for the semiconductor industry. Meeting the image placement metrology demands of accuracy, precision, and measurement speed favors the use of electrical test structures. In this paper, a two-dimensional, modified voltage-dividing potentiometer is applied to a short-loop VLSI process to measure image placement. The contributions of feature placement on the reticle and registration on the wafer to the overall measurement are analyzed and separated. Additional sources of uncertainty are identified, and methods developed to monitor and reduce them are described
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; integrated circuit testing; potentiometers; spatial variables measurement; CMOS/bulk process; electrical test structures; image placement metrology; layer-to-layer feature overlay; overlay metrology; pattern mismatch error; reticle; short-loop VLSI process; voltage-dividing potentiometer; wafer registration; Bridge circuits; CMOS process; Electronics industry; Length measurement; Metrology; NIST; Potentiometers; Silicon; Testing; Voltage;
Conference_Titel :
Microelectronic Test Structures, 1994. ICMTS 1994. Proceedings of the 1994 International Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1757-2
DOI :
10.1109/ICMTS.1994.303504
