A 2.5-3.125 Gb/s quad transceiver with second order analog DLL based CDRs

Author

Coban, Abdulkerim L. ; Koroglu, Mustafa H. ; Ahmed, Kashif A.

Author_Institution

Mindspeed Technol., Inc., Newport Beach, CA, USA

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

143

Lastpage

146

Abstract

This paper describes a 2.5-3.125 Gb/s quad transceiver with second order analog DLL based clock and data recovery (CDR). The proposed CDR can tolerate large frequency offsets with no jitter tolerance degradation. Fabricated in a 0.15 μm CMOS process, the 1.9 mm² transceiver front-end operates from a single 1.2 V supply and consumes 65 mW/channel of which 32 mW is due to the CDR. The CDR jitter generation and high-frequency jitter tolerance are 5.9 psec-rms and 0.5 UI, respectively, when a 3.125 Gb/s 2²³-1 PRBS data with 800 ppm frequency offset is applied.

Keywords

CMOS integrated circuits; delay lock loops; synchronisation; telecommunication links; timing jitter; transceivers; 0.15 micron; 1.2 V; 2.5 to 3.125 Gbit/s; 32 mW; 65 mW; CDR frequency offsets; CDR jitter generation; CMOS; PRBS data; clock and data recovery circuits; jitter tolerance; quad transceiver front-end; second order analog DLL; serial transceivers; Bandwidth; CMOS technology; Clocks; Degradation; Frequency; Jitter; Phase locked loops; Phase shifters; Sampling methods; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358759

Filename

1358759