Design of high-performance asynchronous sigma delta modulators with a binary quantizer with hysteresis

Author

Ouzounov, S. ; Roza, E. ; Hegt, H. ; van der Weide, G. ; van Roermund, A.

Author_Institution

Eindhoven Univ. of Technol., Netherlands

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

181

Lastpage

184

Abstract

This work describes the design of asynchronous sigma delta modulators (ASDMs) with a binary quantizer with hysteresis. The ASDM is treated as a closed loop non-linear system that operates using an inherent limit cycle. A first and a second order ASDM have been implemented in a digital 0.18 μm CMOS technology. The measured SFDR is 75 dB in a frequency band of 8 MHz for the first-order and 72 dB in a band of 12 MHz for the second-order ASDM.

Keywords

CMOS integrated circuits; VHF circuits; asynchronous circuits; circuit feedback; hysteresis; quantisation (signal); sigma-delta modulation; 0.18 micron; 12 MHz; 120 MHz; 140 MHz; 8 MHz; SFDR; asynchronous sigma delta modulators; binary quantizer; closed loop nonlinear system; digital CMOS technology; first-order ASDM; inherent limit cycle; quantizer hysteresis; second-order ASDM; Delta modulation; Delta-sigma modulation; Equations; Feedback circuits; Frequency; Hysteresis; Laboratories; Limit-cycles; Space vector pulse width modulation; Variable speed drives;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358770

Filename

1358770