1948117

Interconnect Design Strategy for High-Speed Logic LSIs

Yamashina, Masakazu ; Mizuno, Masayuki ; Shibayama, Atsufumi

NEC, Japan

1

1999

13-15 Sept. 1999

11

16

CMOS logic circuits; Clocks; Delay estimation; Frequency; Integrated circuit interconnections; Large scale integration; Logic design; Technological innovation; Wire; Wiring;

English

ieee

Solid-State Device Research Conference, 1999. Proceeding of the 29th European

Leuven, Belgium

2-86332-245-1

conf

1505443