Low area memory-free FPGA implementation of the AES algorithm

A new FPGA design for the Advanced Encryption Standard (AES) is presented in this paper. This design is believed to be the smallest memory free FPGA implementation of the AES encryption only requiring 184 slices on a Xilinx Spartan 3 (XC3S50) device, and 80 slices on a Spartan 6 (XC6SLX4) device while achieving throughputs of 36.5Mbps and 58.13Mbps respectively. This FPGA design adopts an 8-bit architecture and exploits the specific fabric in Spartan 3 and Spartan 6 generation FPGAs to optimize the implementation of the shifting operations.