Title :
Low area memory-free FPGA implementation of the AES algorithm
Author :
Chu, Junfeng ; Benaissa, Mohammed
Author_Institution :
Dept. of Electron. & Electr. Eng., Univ. of Sheffield, Sheffield, UK
Abstract :
A new FPGA design for the Advanced Encryption Standard (AES) is presented in this paper. This design is believed to be the smallest memory free FPGA implementation of the AES encryption only requiring 184 slices on a Xilinx Spartan 3 (XC3S50) device, and 80 slices on a Spartan 6 (XC6SLX4) device while achieving throughputs of 36.5Mbps and 58.13Mbps respectively. This FPGA design adopts an 8-bit architecture and exploits the specific fabric in Spartan 3 and Spartan 6 generation FPGAs to optimize the implementation of the shifting operations.
Keywords :
cryptography; field programmable gate arrays; AES algorithm; Spartan 6 device; XC3S50 device; XC6SLX4 device; Xilinx Spartan 3 device; advanced encryption standard; byte rate 36.5 MByte/s; byte rate 58.13 MByte/s; low area memory-free FPGA implementation; shifting operations; word length 8 bit; Clocks; Computer architecture; Encryption; Field programmable gate arrays; Hardware; Shift registers; Throughput;
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
Conference_Location :
Oslo
Print_ISBN :
978-1-4673-2257-7
Electronic_ISBN :
978-1-4673-2255-3
DOI :
10.1109/FPL.2012.6339250
