Fast digital rendering for special effects

Photo-realistic rendering required for movie special effects is computationally intensive, keeping large server clusters occupied for months. To speed up this process, some key modules, in particular the ray-triangle intersection (RTI) test, have been implemented on an FPGA. Although the FPGA was able to speed up the RTI test by a factor of two, the PCIe bus is not fast enough to keep the RTI pipeline full. Several further enhancements to Reyes pipeline implementation have been proposed and preliminary calculations showed that they can reduce the bottleneck by a factor of ~ 300.