Title :
Low power logic circuit and SRAM cell applications with silicon on depletion layer CMOS (SODEL CMOS) technology
Author :
Inaba, S. ; Nagano, Hidehisa ; Miyano, K. ; Mizushima, I. ; Okayama, Y. ; Nakauchi, T. ; Ishimaru, K. ; Ishiuchi, H.
Author_Institution :
SoC Res. & Dev. Center, Toshiba Corp. Semicond. Co., Yokohama, Japan
Abstract :
In this paper, the AC performance of SODEL CMOS is discussed, aiming for low power CMOS applications. Propagation delay time (τpd) in SODEL CMOS has been improved by up to 25 % in five stacked nFET inverters, and about 30% better power-delay product has been observed at same τpd, compared to conventional (conv.) bulk CMOS. In SRAM cell applications of SODEL CMOS, a high SNM of ∼95 mV was observed at Vdd = 0.6 V. Smaller bitline delay is confirmed by SPICE simulations. Latch-up immunity for α-particles was found to be comparable to conv. bulk CMOS. Therefore, SODEL CMOS technology will give us better solutions for low power SoCs.
Keywords :
CMOS logic circuits; SRAM chips; alpha-particle effects; logic gates; low-power electronics; system-on-chip; 0.6 V; 95 mV; SNM; SODEL CMOS; SRAM cells; Si; alpha particle latch-up immunity; bitline delay; low power SoC; low power logic circuits; power-delay product; propagation delay time; silicon on depletion layer CMOS; stacked nFET inverters; CMOS logic circuits; CMOS memory circuits; CMOS process; CMOS technology; FETs; Implants; Logic circuits; Random access memory; SPICE; Silicon;
Conference_Titel :
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Print_ISBN :
0-7803-8495-4
DOI :
10.1109/CICC.2004.1358783
