Multi-kernel floorplanning for enhanced CGRAS

Signal processing applications have been shown to map well to time multiplexed coarse grained reconfigurable array (CGRA) devices, and can often be decomposed into a set of communicating kernels. This decomposition can facilitate application development and reuse but has significant consequences for tools targeting these devices in terms of allocation and arrangement of resources. This paper presents a CGRA floorplanner to optimize the division and placement of resources for multi-kernel applications. The task is divided into two phases aligned with the respective goals. Resource allocation is accomplished through incremental assignment to minimize performance bottlenecks while operating within the bounds of the maximum available resources. The resulting allocation of resources is arranged in the device using simulated annealing and a perimeter-based cost function which serves to minimize resources needed for both interand intra-kernel communications. The floorplanner is applied to a set of multi-kernel benchmarks demonstrating resource allocations providing maximum throughput across a range of available resources. The algorithms are very fast, taking only a few seconds while producing high quality results. Inter-kernel wire lengths are almost always minimal, and the resource allocation is proven optimal.