MOSFET scaling trends and challenges through the end of the roadmap

Author

Zeitzoff, Peter M.

Author_Institution

Int. SEMATECH, Austin, TX, USA

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

233

Lastpage

240

Abstract

The overall trends and issues in logic MOSFET scaling are discussed from the perspective of the 2003 International Technology Roadmap for Semiconductors. Critical challenges with scaling include increasing gate leakage current and polysilicon gate depletion, difficulty in controlling short channel effects, etc. Key innovations to address these challenges include high-k gate dielectric, metal gate electrode, strained silicon channel for enhanced mobility, and eventually, non-classical CMOS devices (e.g., FinFETs).

Keywords

CMOS logic circuits; MOSFET; carrier mobility; dielectric thin films; leakage currents; low-power electronics; CMOS devices; FinFET; enhanced mobility strained silicon channels; gate leakage current; high-k gate dielectrics; high-performance logic; logic MOSFET scaling trends; low-power logic; metal gate electrodes; polysilicon gate depletion; short channel effects; CMOS technology; Cost function; Electrodes; Leakage current; Logic devices; MOSFET circuits; Power MOSFET; Power dissipation; Semiconductor materials; Technological innovation;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358785

Filename

1358785

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1948414