DocumentCode
1948466
Title
Convey vector personalities - FPGA acceleration with an openmp-like programming effort?
Author
Meyer, Björn ; Schumacher, Jörn ; Plessl, Christian ; Förstner, Jens
Author_Institution
Paderborn Center for Parallel Comput., Univ. of Paderborn, Paderborn, Germany
fYear
2012
fDate
29-31 Aug. 2012
Firstpage
189
Lastpage
196
Abstract
Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMP-like directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.
Keywords
field programmable gate arrays; logic design; message passing; parallel programming; FPGA acceleration; OpenMP-like programming; computational nanophotonics; convey HC-1 reconfigurable computer; convey vector personality; hardware design methods; optimized OpenMP-parallelized CPU; scientific code acceleration; socket quad-core server; Acceleration; Computational modeling; Coprocessors; Field programmable gate arrays; Memory management; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
Conference_Location
Oslo
Print_ISBN
978-1-4673-2257-7
Electronic_ISBN
978-1-4673-2255-3
Type
conf
DOI
10.1109/FPL.2012.6339259
Filename
6339259
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