DocumentCode :
1948486
Title :
Cost-competitive RF wafer test methodology for high volume production of complex RF ICs
Author :
Paganini, Andrea ; Slamani, Mustapha ; Ding, Hanyi ; Ferrario, John ; Na, Nanju
Author_Institution :
IBM Syst. & Technol. Group, Essex Junction, VT
fYear :
2008
fDate :
27-30 May 2008
Firstpage :
1256
Lastpage :
1264
Abstract :
The need for radio frequency (RF) test at the wafer level in high-volume production has increased in response to the growing demand for delivering complex "good known dies" (KGD). To keep pace with the market, innovative test solutions need to be developed to meet tighter electrical specifications while maximizing yields and profit margins. This paper presents a versatile test platform built upon low- cost, custom circuitry combined with high performance membrane probes to achieve the lowest test cost per die. In a case study for testing global positioning system (GPS) RF integrated circuit (IC) the proposed methodology implements a quad-site solution to demonstrate superior test time and accuracy compared to traditional approaches.
Keywords :
Global Positioning System; integrated circuit testing; radiofrequency integrated circuits; wafer level packaging; Global Positioning System testing; RF IC; cost-competitive RF wafer test methodology; radio frequency integrated circuit; radio frequency test; versatile test platform; wafer level package; Biomembranes; Circuit testing; Costs; Integrated circuit testing; Integrated circuit yield; Probes; Production; Radio frequency; Radiofrequency integrated circuits; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2008. ECTC 2008. 58th
Conference_Location :
Lake Buena Vista, FL
ISSN :
0569-5503
Print_ISBN :
978-1-4244-2230-2
Electronic_ISBN :
0569-5503
Type :
conf
DOI :
10.1109/ECTC.2008.4550136
Filename :
4550136
Link To Document :
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