Title :
Dataflow graph partitioning for high level synthesis
Author :
Sinha, Sharad ; Srikanthan, Thambipillai
Author_Institution :
Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
This paper presents a dataflow graph (DFG) partitioning methodology for effective high level synthesis in the presence of constraints like data initiation interval (II) and area. It also focuses on handling large DFGs for high level synthesis with area reduction as a requirement. An algorithm for dataflow graph partitioning is presented that aims to reduce area utilization as well as ensure that data initiation interval constraint is met. The algorithm works so as to fit a design into the design space between fully pipelined design and fully resource shared design in order to meet the initiation interval constraint and reduce area only as much as required compared to a fully pipelined design where the area is wasted in the presence of II constraint and a fully resource shared design where the extreme reduction in area puts additional unnecessary constraint on data initiation interval.
Keywords :
C++ language; data flow graphs; data reduction; electronic design automation; high level synthesis; C based high level synthesis; C++ based high level synthesis; DFG; area reduction; area utilization reduction; data initiation interval constraint; dataflow graph partitioning methodology; fully pipelined design; fully resource shared design; Algorithm design and analysis; Benchmark testing; Clocks; Hardware; High level synthesis; Partitioning algorithms; Resource management;
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
Conference_Location :
Oslo
Print_ISBN :
978-1-4673-2257-7
Electronic_ISBN :
978-1-4673-2255-3
DOI :
10.1109/FPL.2012.6339265