A fast and high quality stereo matching algorithm on FPGA

In this paper, we describe an FPGA stereo vision system with lower error rate and high processing speed. In our system, two algorithms, the cost aggregation and fast locally consistent dense stereo, are used to achieve the lower error rate on the pipelined circuit while maintaining the high processing speed. We have evaluated the performance of the circuit on Xilinx Vertex-6 FPGAs. Its error rate is competitive with the top-level software algorithms, and its processing speed is almost 2 clock cycles per pixel, which reaches to 507.4 fps for 640 × 480 pixel images.