Raising the abstraction level of HDL for control-dominant applications

As the complexity of modern digital systems continues to increase exponentially, the need for beyondRTL design methodologies is growing as well. In this paper, we propose a high-level hardware description language that allows the user to dynamically modify and constrain the connections between data token sources and sinks. Actual transfers occur when both sources and sinks are ready to proceed, according to different predefined synchronization protocols. At this level of abstraction, both FSM programming and constraint programming paradigms are combined to enhance the user´s ability to describe and exploit fine-grain parallelismin control-intensive hardware designs. The proposed hardware description methodology is applied to the description of two hardware implementations of the QuickSort algorithm, using pipelined memory and comparator components.