Proactive design for manufacturing (DFM) for nanometer SoC designs

In this paper, we propose an innovative DFM design flow which achieves designs for logic products that are much more manufacturable than those using traditional design flows in nm technologies. It integrates manufacturability information-extracted directly from the target nm process-into the timing-driven synthesis and P&R cost function. It has three major elements: 1) A DFM extension library, which creates "yield strength" variants of the basic logic functions in the library; 2) a new design view data-file, containing a pre-characterized set of design attributes extracted from the cell library layouts and the required target process parameter extractions; 3) a set of software elements that plug the manufacturability information into the standard IC design creation and analysis flow. The EDA tools interact with these elements to determine the most manufacturable mapping and arrangement of any given logic function onto the physical library.