Author :
Khan, A. ; Ruparel, K. ; Joly, C. ; Ghanta, V. ; Le, D. ; Nguyen, T. ; Yu, J. ; Yang, S. ; Ahmed, I. ; Burnside, N. ; Chagarlamudi, V. ; Cheung, M. ; Chiu, F. ; Fan, Y. ; Ge, D. ; Gill, J. ; Huang, P. ; Jayapal, V. ; Kim, O. ; Li, M. ; Mak, H. ; McKeever,
Author_Institution :
Cadence Design Syst. Inc., San Jose, CA, USA
Abstract :
A system-centric, fully-hierarchical design methodology and design techniques developed to create four ICs, which provide the core functionality of a multi-Gigabit switching network system, are presented. The system is capable of switching more than 500 million packets per second. Electrical and physical design methods for one IC are described. ∼76 M transistors are integrated in a 130 nm CMOS 8-metal process. Functional and electrical design requirements were achieved with the first silicon.
Keywords :
CMOS integrated circuits; integrated circuit design; packet switching; switching circuits; switching networks; 130 nm; CMOS; multiGigabit switching network system; packet networking systems; system-centric fully-hierarchical design; Assembly systems; Buffer storage; CMOS process; Control systems; Design methodology; Engines; Packaging; Packet switching; Signal design; Throughput;
