DocumentCode
1948980
Title
Logic simulation on vector processors
Author
Raghavan, R. ; Hayes, J.P. ; Martin, W.R.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fYear
1988
fDate
7-10 Nov. 1988
Firstpage
268
Lastpage
271
Abstract
The performance of three commercial vector computers, the Cray X-MP/48, IBM 3090/400, and Alliant FX/8, for simulating logic circuits at gate level is compared. Experiments that assume zero- and unit-delay models demonstrate that certain key architectural features, especially, the presence of a scalar cache, have an adverse impact on the potential speedup. Consequently, the achievable speedup due to vectorization of simulation code, while still substantial, is less than expected. The results indicate that concurrent operation of multiple CPUs in vector mode in machines such as the Alliant FX/8 might be the most cost-effective speedup technique for logic simulation on current vector processors.<>
Keywords
computer evaluation; logic CAD; parallel architectures; parallel machines; performance evaluation; Alliant FX/8; Cray X-MP/48; IBM 3090/400; achievable speedup; code vectorization; commercial vector computers; concurrent operation; gate level logic circuit simulation; key architectural features; multiple CPUs; potential speedup; scalar cache; simulation code; speedup technique; unit-delay models; vector mode; vector processors; zero-delay models; Circuit simulation; Computational modeling; Computer architecture; Computer simulation; Logic circuits; Logic design; Logic testing; Registers; Vector processors; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-0869-2
Type
conf
DOI
10.1109/ICCAD.1988.122508
Filename
122508
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