Title :
Discrete-event simulation on hypercube architectures
Author :
Chamberlain, R.D. ; Franklin, M.A.
Author_Institution :
Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA
Abstract :
A performance model for a hierarchical discrete-event-simulation algorithm running on a hypercube architecture is presented. A static allocation of system components to hypercube processors and a global clock algorithm with an event-based time increment are assumed. The model is applied to a digital systems simulation. The effects of different architectures, algorithm parameter values, and partitioning strategies on speedup are evaluated.<>
Keywords :
parallel architectures; performance evaluation; virtual machines; algorithm parameter values; digital systems simulation; event-based time increment; global clock algorithm; hierarchical discrete-event-simulation algorithm; hypercube architecture; hypercube processors; partitioning strategies; performance model; speedup; static allocation; system components; Algorithm design and analysis; Clocks; Computer architecture; Digital systems; Discrete event simulation; Hypercubes; Parallel architectures; Parallel processing; Partitioning algorithms; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122509
