Title :
Timing optimization of combinational logic
Author :
Singh, K.J. ; Wang, A.R. ; Brayton, R.K. ; Sangiovanni-Vincentelli, A.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
An algorithm for speeding up combinational logic with minimal area increase is presented. A static timing analyzer is used to identify the critical paths. Then a weighted min-cut algorithm is used to determine the subset of nodes to be resynthesized. This subset is selected so that the speedup is achieved with minimal area increase. Resynthesis is done by selectively collapsing the logic along the critical paths and then decomposing the collapsed nodes to minimize the critical delay. This process is iterated until either the timing requirements are satisfied or no further improvement can be made. The algorithm has been implemented and tested on many design examples with promising results.<>
Keywords :
combinatorial circuits; logic CAD; collapsed nodes; combinational logic timing optimization; critical delay; critical paths; minimal area increase; node resynthesis; static timing analyzer; weighted min-cut algorithm; Added delay; Circuit topology; Libraries; Logic circuits; Logic devices; Petroleum; Process design; Silicon; Tellurium; Timing;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122511
