Hybrid approach to structured ASICs for minimizing the impact of reticle costs and interconnect delay

System designers face an ever more complex set of tradeoffs in developing advanced digital systems. Transistors are getting faster, interconnect is getting slower, signal integrity issues are getting more complex, and reticle costs are exploding at an exponential rate. This paper takes a look at a unique hybrid processing approach for structured ASICs which reduces reticle costs and avoids many of the interconnect issues associated with ultra-deep sub-micron (UDSM) processes. In particular it investigates the impact of reduced programmable interconnect levels on routing congestion and performance relative to comparable cell-based ASIC technologies. Two designs are used to compare structured ASICs to a 180nm standard cell technology. The comparison metrics include maximum clock rate, density, area, clock latency, clock skew and CT fan out.