Title :
Hybrid approach to structured ASICs for minimizing the impact of reticle costs and interconnect delay
Author :
Brown, Jim ; Packer, Reed ; Prasad, Jagdish ; Kofford, Khris ; Dye, Troy ; Kirk, Bob
Author_Institution :
AMI Semicond., Inc., Pocatello, ID, USA
Abstract :
System designers face an ever more complex set of tradeoffs in developing advanced digital systems. Transistors are getting faster, interconnect is getting slower, signal integrity issues are getting more complex, and reticle costs are exploding at an exponential rate. This paper takes a look at a unique hybrid processing approach for structured ASICs which reduces reticle costs and avoids many of the interconnect issues associated with ultra-deep sub-micron (UDSM) processes. In particular it investigates the impact of reduced programmable interconnect levels on routing congestion and performance relative to comparable cell-based ASIC technologies. Two designs are used to compare structured ASICs to a 180nm standard cell technology. The comparison metrics include maximum clock rate, density, area, clock latency, clock skew and CT fan out.
Keywords :
application specific integrated circuits; delays; integrated circuit design; integrated circuit interconnections; integrated circuit measurement; logic design; logic testing; network routing; programmable logic devices; reconfigurable architectures; reticles; 180 nm; CT fan out; cell-based ASIC technologies; chip area; chip density; clock latency; clock skew; comparison metrics; design tradeoffs; digital systems; hybrid processing approach; hybrid system design; interconnect delay; interconnects; maximum clock rate; reduced programmable interconnect levels; reticle costs; routing congestion; signal integrity; standard cell technology; structured ASIC; transistor speed; ultra-deep sub-micron processes; Application specific integrated circuits; Circuit testing; Clocks; Costs; Delay; Field programmable gate arrays; Integrated circuit interconnections; Packaging; Production; Routing;
Conference_Titel :
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Print_ISBN :
0-7803-8495-4
DOI :
10.1109/CICC.2004.1358841