• DocumentCode
    1949577
  • Title

    C4NP technology: Manufacturability, yields and reliability

  • Author

    Perfecto, Eric D. ; Hawken, David ; Longworth, Hai P. ; Cox, Harry ; Srivastava, Kamalesh ; Oberson, Valerie ; Shah, Jayshree ; Garant, John

  • Author_Institution
    IBM Syst. & Technol. Group (STG), Hopewell Junction, NY
  • fYear
    2008
  • fDate
    27-30 May 2008
  • Firstpage
    1641
  • Lastpage
    1647
  • Abstract
    As a part of IBM movement from Pb-rich solders to Pb-free solder, a new low cost process has been developed to deposit the solder to a capture, or under bump metal (UBM) pad, with Suss MicroTech Inc as the equipment partner. The controlled collapsed chip connection new process (C4NP) has moved, over the last 2 years, from development into manufacturing for 300 mm wafers. During this transition, a great number of process improvements have resulted in high fabrication yields. Manufacturing robustness has been achieved by clearly identifying the processes which affect the C4 structural integrity. The solder composition has been optimized to improve its mechanical properties as well as low alpha emission rate requirement. Sector partitioning methodology was used to obtain root cause for various defects which then, through replication studies, were confirmed. Key process improvements in the capture pad build, mold fabrication, and mold fill tool have been accomplished as the process has matured. Thermal undercut was identified as a mechanism of Cu seed consumption when no top Cu was available on top of the Ni UBM. C4NP technology can produce yields comparable to that of electroplated C4 Bumps. Yield learning model shows a 15% defect reduction per month since the start of the C4NP program. Technology qualification for 300 mm wafers with 200um and 150 um pitch Pb-free C4 bumps has been successfully completed.
  • Keywords
    electronics packaging; integrated circuit reliability; mechanical properties; moulding; soldering; C4NP technology; capture pad build; controlled collapsed chip connection new process; fabrication yield; manufacturability; mechanical property; mold fabrication; mold fill tool; reliability; sector partitioning; solder composition; under bump metal; yield learning; Closed loop systems; Costs; Environmentally friendly manufacturing techniques; Fabrication; Lead; Manufacturing processes; Mechanical factors; Qualifications; Robustness; Semiconductor device modeling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2008. ECTC 2008. 58th
  • Conference_Location
    Lake Buena Vista, FL
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-4244-2230-2
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2008.4550197
  • Filename
    4550197