DocumentCode
1949652
Title
MAX II: A low-cost, high-performance LUT-based CPLD
Author
Leventis, Paul ; Vest, Brad ; Hutton, Michael ; Lewis, David
Author_Institution
Altera Corp., San Jose, CA, USA
fYear
2004
fDate
3-6 Oct. 2004
Firstpage
443
Lastpage
446
Abstract
This paper describes the MAX II CPLD architecture. Departing from traditional CPLD product-term logic elements and global routing, it instead employs FPGA-like look-up tables and channel-based routing. It integrates a flash memory for configuration and a voltage regulator for core power flexibility, and delivers 2.9× higher logic density, 2.2× greater performance, and consumes >15× less power in 1/6 the die size of its predecessor, the MAX 7000A.
Keywords
flash memories; integrated memory circuits; logic design; network routing; programmable logic devices; table lookup; voltage regulators; FPGA-like look-up tables; MAX II CPLD architecture; MAX II low-cost high-performance LUT-based CPLD; channel-based routing; complex programmable logic devices; core power flexibility; die size; global routing; integrated flash memory; logic density; power consumption; product-term logic elements; voltage regulator; Decoding; Delay; Fabrics; Flash memory; Logic design; Logic devices; Macrocell networks; Routing; Scalability; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Print_ISBN
0-7803-8495-4
Type
conf
DOI
10.1109/CICC.2004.1358846
Filename
1358846
Link To Document