Title :
A pipeline parallel architecture for a fuzzy inference processor
Author :
Ascia, Giuseppe ; Catania, Vincenzo
Author_Institution :
Ist. di Inf. e Telecommun., Catania Univ., Italy
Abstract :
The paper presents the architecture of a VLSI processor for applications based on fuzzy logic. The main features of the architecture are: a pre-computation phase of the positive degree of truth of the antecedent with fuzzy inputs; a detection phase of the rules positive degree of activation, parallelism in some phases of inference which is split into a sequence of pipeline stages. The processing speed is up to 16.7 MFLIPS for inferences with 64 rules with 4 linguistic variables
Keywords :
fuzzy logic; inference mechanisms; parallel architectures; pipeline processing; activation; detection phase; fuzzy inference processor; fuzzy logic; pipeline parallel architecture; Computer architecture; Concurrent computing; Delay; Fuzzy logic; Fuzzy sets; Fuzzy systems; Hardware; Parallel architectures; Parallel processing; Pipelines;
Conference_Titel :
Fuzzy Systems, 2000. FUZZ IEEE 2000. The Ninth IEEE International Conference on
Conference_Location :
San Antonio, TX
Print_ISBN :
0-7803-5877-5
DOI :
10.1109/FUZZY.2000.838668
