Study on Detecting of Competition Phenomena of Signal for Logic Combinational Circuit

Competition phenomena of signal is very important for the stability of logical combinational circuit. This paper presents a novel method for detecting the gates where glitches might exist in digital circuits. For these gates, the glitches are partly caused by the different delay time of the gate´s input signals. At first, the modeling is to divide the gates into different levels according to the path length of their outputs, using graph theory. Then, an algorithm is proposed to compute the delay time of each gate´s output signal in the circuit. Besides the modeling method and algorithm, a software is offered to simulate the method by inputing the conjunction matrix and delay time matrix of the digital circuit. A example is given at then end of this paper. This method, including the modeling, the algorithm and the software, is based on graph theory and very simple