• DocumentCode
    1950092
  • Title

    BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing

  • Author

    Grigorian, Beayna ; Farahpour, Nazanin ; Reinman, Glenn

  • Author_Institution
    Comput. Sci. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA
  • fYear
    2015
  • fDate
    7-11 Feb. 2015
  • Firstpage
    615
  • Lastpage
    626
  • Abstract
    Applications with large amounts of data, real-time constraints, ultra-low power requirements, and heavy computational complexity present significant challenges for modern computing systems, and often fall within the category of high performance computing (HPC). As such, computer architects have looked to high performance single instruction multiple data (SIMD) architectures, such as accelerator-rich platforms, for handling these workloads. However, since the results of these applications do not always require exact precision, approximate computing may also be leveraged. In this work, we introduce BRAINIAC, a heterogeneous platform that combines precise accelerators with neural-network-based approximate accelerators. These reconfigurable accelerators are leveraged in a multi-stage flow that begins with simple approximations and resorts to more complex ones as needed. We employ high-level, application-specific light-weight checks (LWCs) to throttle this multi-stage acceleration flow and reliably ensure user-specified accuracy at runtime. Evaluation of the performance and energy of our heterogeneous platform for error tolerance thresholds of 5%-25% demonstrates an average of 3× gain over computation that only includes precise acceleration, and 15×-35× gain over software-based computation.
  • Keywords
    approximation theory; neural nets; parallel architectures; BRAINIAC; HPC; SIMD architecture; accelerator-rich platform; application-specific light-weight check; high performance computing; multistage acceleration flow; neural-network-based approximate accelerator; neurally-implemented approximate computing; real-time constraint; single instruction multiple data; Acceleration; Approximation methods; Artificial neural networks; Benchmark testing; Hardware; RNA; Software;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture (HPCA), 2015 IEEE 21st International Symposium on
  • Conference_Location
    Burlingame, CA
  • Type

    conf

  • DOI
    10.1109/HPCA.2015.7056067
  • Filename
    7056067