Title :
Understanding contention-based channels and using them for defense
Author :
Hunger, Casen ; Kazdagli, Mikhail ; Rawat, Ankit ; Dimakis, Alex ; Vishwanath, Sriram ; Tiwari, Mohit
Author_Institution :
Univ. of Texas at Austin, Austin, TX, USA
Abstract :
Microarchitectural resources such as caches and predictors can be used to leak information across security domains. Significant prior work has demonstrated attacks and defenses for specific types of such microarchitectural side and covert channels. In this paper, we introduce a general mathematical study of microarchitectural channels using information theory. Our conceptual contribution is a simple mathematical abstraction that captures the common characteristics of all microarchitectural channels. We call this the Bucket model and it reveals that microarchitectural channels are fundamentally different from side and covert channels in networking. We then quantify the communication capacity of several microarchitectural covert channels (including channels that rely on performance counters, AES hardware and memory buses) and measure bandwidths across both KVM based heavy-weight virtualization and light-weight operating-system level isolation. We demonstrate channel capacities that are orders of magnitude higher compared to what was previously considered possible. Finally, we introduce a novel way of detecting intelligent adversaries that try to hide while running covert channel eavesdropping attacks. Our method generalizes a prior detection scheme (that modeled static adversaries) by introducing noise that hides the detection process from an intelligent eavesdropper.
Keywords :
cache storage; computer architecture; information theory; microprocessor chips; security of data; AES hardware; Bucket model; KVM based heavy-weight virtualization; bandwidths measurement; caches; channel capacities; communication capacity; contention-based channels; covert channel eavesdropping attacks; defenses; information leak; information theory; intelligent eavesdropper; light-weight operating-system level isolation; mathematical abstraction; memory buses; microarchitectural covert channels; microarchitectural resources; microarchitectural side channels; networking; performance counters; predictors; security domains; static adversaries; Clocks; Hardware; Microarchitecture; Probes; Radiation detectors; Receivers; Synchronization;
Conference_Titel :
High Performance Computer Architecture (HPCA), 2015 IEEE 21st International Symposium on
Conference_Location :
Burlingame, CA
DOI :
10.1109/HPCA.2015.7056069