DocumentCode

1950157

Title

Closed-Loop CMOS Gate Delay Time Optimization

Author

Stockinger, Michael ; Selberherr, Siegfried

Author_Institution

Vienna University of Technology, Austria

Volume

1

fYear

1999

fDate

13-15 Sept. 1999

Firstpage

504

Lastpage

507

Keywords

CMOS technology; Capacitance; Containers; Delay effects; Doping profiles; Inverters; Leakage current; MOSFETs; Microelectronics; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 1999. Proceeding of the 29th European

Conference_Location

Leuven, Belgium

Print_ISBN

2-86332-245-1

Type

conf

Filename

1505550