A CMOS high efficiency +22 dBm linear power amplifier

Author

Ding, Yongwang ; Harjani, Ramesh

Author_Institution

Bermai Inc., Minnetonka, MN, USA

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

557

Lastpage

560

Abstract

Modern wireless communication systems require power amplifiers with high efficiency and high linearity. CMOS is the technology of choice for complete systems on a chip due to its lower costs and high integration levels. However, in the past it has always been difficult to integrate high efficiency power amplifiers in CMOS. In this paper, we present a new class of operation (parallel A&B) for power amplifiers that improves both their dynamic range and power efficiency. A prototype design of the new amplifier was fabricated in a 0.18 μm CMOS technology. The measurement results show over 44% PAE and +22 dBm output power. In comparison to a normal class A amplifier, this new design increases the P1dB by over 3 dB and yet reduces DC power consumption by up to 50% in the linear operation range.

Keywords

CMOS analogue integrated circuits; linearisation techniques; power amplifiers; radiofrequency amplifiers; radiofrequency integrated circuits; 0.18 micron; 44 percent; CMOS high efficiency PA; high linearity power amplifiers; linear RF power amplifier; parallel class A/B operation; wireless communication systems; CMOS technology; Costs; Dynamic range; High power amplifiers; Linearity; Operational amplifiers; Power amplifiers; Power measurement; Prototypes; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358883

Filename

1358883