• DocumentCode
    1950412
  • Title

    Development and evaluation of lead free reflow soldering techniques for the flip chip bonding of large GaAs pixel detectors on Si readout chip

  • Author

    Klein, M. ; Hutter, M. ; Oppermann, H. ; Fritzsch, T. ; Engelmann, G. ; Dietrich, L. ; Wolf, J. ; Brämer, B. ; Dudek, R. ; Reichl, H.

  • Author_Institution
    Fraunhofer-Inst. fur Zuverlassigkeit und Mikrointegration, Tech. Univ. Berlin, Berlin
  • fYear
    2008
  • fDate
    27-30 May 2008
  • Firstpage
    1893
  • Lastpage
    1899
  • Abstract
    Lead free reflow soldering techniques applying AuSn as well as SnAg electroplated bumps were chosen for the evaluation of the flip chip bonding process for a x-ray pixel detector. Both can be used in pick & place processes with a subsequent batch reflow suitable for high volume production. AuSn solder was selected due to its fluxless bondability, the good wettability and the self-alignment process capability and SnAg solder due to its more ductile behaviour and lower yield stress compared to AuSn. GaAs test chips with daisy chain and four point Kelvin probe structures together with appropriate Si test substrates were designed, manufactured and bumped. Test chips with 55 and 170 mum pitch and different chip sizes (maximum 16.3 down to 4 mm square) were used. AuSn bumps were deposited by electroplating Au first and Sn on top. Au bumps were also formed on substrate side. Two under bump metallizations (UBM) were used for the SnAg samples: Cu and Ni. FE simulation was performed for AuSn and SnAg interconnections and for different chip sizes. A local model was designed for the bump interconnection and a global octant model for the whole assembly. Very high values were calculated for the peel stress using AuSn bumps. SnAg bumps on the other hand showed a 3 to 5 times reduced peel stress dependent on the chip size. A flip chip bonding process setup was carried out for both solder types, AuSn as well as SnAg, with an analysis of the samples by electrical measurements, cross sectioning and SEM. Due to the different coefficients of the thermal expansion (CTE) of GaAs and Si no stable bonding process was found for the AuSn modules as predicted by the FE analysis. With increasing chip size failures like pad lift or cracking of the GaAs were observed. The SnAg samples showed good bonding results. This technology was then selected to assemble test modules for thermal cycling between -55 and +125degC comparing the Cu and Ni UBM. The modules were qualified by electrical monitor- ing as well as cross sectioning. More than 200 cycles were reached by the 55 mum pitch, 16.3 mm square, bonded GaAs chips and about 400 by the smallest, 4 mm square chips, although no underfilling was used. As failure mode a fracture within the solder was detected. Based on experimental and simulation results functional 256 times256 GaAs pixel detectors with a chip size of 14 times14 mm2 were assembled on Si read out chips using SnAg bumps on a Cu UBM. Finally, these x-ray image sensors were wire bonded to a PCB and successfully tested showing a yield (on pixel-level) of about 98%.
  • Keywords
    III-V semiconductors; elemental semiconductors; flip-chip devices; gallium arsenide; reflow soldering; silicon; tin compounds; GaAs; Kelvin probe structures; PCB; SnAg; X-ray pixel detector; electroplated bumps; flip chip bonding; lead free reflow soldering; pixel detectors; readout chip; Assembly; Bonding processes; Detectors; Environmentally friendly manufacturing techniques; Flip chip; Gallium arsenide; Lead; Reflow soldering; Stress; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2008. ECTC 2008. 58th
  • Conference_Location
    Lake Buena Vista, FL
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-4244-2230-2
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2008.4550240
  • Filename
    4550240