• DocumentCode
    1950432
  • Title

    Effect of organic package warpage and assembly challenges using thin core substrate

  • Author

    Dubey, Ajit

  • Author_Institution
    NetLogic Microsyst., Mountain View, CA
  • fYear
    2008
  • fDate
    27-30 May 2008
  • Firstpage
    1907
  • Lastpage
    1912
  • Abstract
    The need for thin core substrates is increasing in the industry to meet low inductance. However, there are major challenges of reducing thin core substrate warpage in assembly which needs thorough understanding of the assembly process steps and its effect on warpage. There are various assembly stages that influence the package warpage as a result of time and temperature. Reflow process during die attach, underfill curing and lid attach process play a significant role in package warpage. Substrate manufacturers typically provide substrate warpage of 4 mils max which does not allow much margin left in assembly considering the number of reflows and curing profiles the package undergoes during assembly. This paper illustrates the warpage at each assembly process step and its impact on assembly yield and reliability with 400 um thin core 27 x 27 mm, 4-2-4 package. In this paper, package warpage at various reflow profiles, underfill curing profiles and lid attach processes has been evaluated. The warpage studies are carried out on a flip chip organic BGA package with underfill and a single piece lid using a 400 um thin core substrate. The package also comprises of low k layers which is another challenge that is explored to ensure the reliability of low k delaminations on a thin core substrate. The challenges are increased further since the package also needs to qualify board level reliability in addition to level 1 qualification. The paper also illustrates the board level reliability tests and its qualification results.
  • Keywords
    ball grid arrays; chip-on-board packaging; curing; delamination; flip-chip devices; integrated circuit bonding; integrated circuit packaging; integrated circuit testing; integrated circuit yield; low-k dielectric thin films; microassembling; substrates; assembly process steps; board level reliability tests; die attach; flip chip organic package warpage; lid attach process; low k delaminations; reflow process; size 400 mum; thin core substrates; underfill curing profiles; Assembly; Curing; Delamination; Flip chip; Inductance; Manufacturing; Microassembly; Packaging; Qualifications; Temperature;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2008. ECTC 2008. 58th
  • Conference_Location
    Lake Buena Vista, FL
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-4244-2230-2
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2008.4550242
  • Filename
    4550242