A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors

Author

Bae, Young-Don ; Park, In-Cheol

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon, South Korea

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

583

Lastpage

586

Abstract

This paper describes a configurable platform chip integrating 9 heterogeneous processors, which is designed to enable rapid prototyping and verification without translating functional behaviors into hardware blocks. The chip consists of a 32-bit multithreaded RISC processor for fast context switching, four 32-bit SIMD processors for data-intensive applications, and four IO processors for handling I/O protocols. The prototype chip has been designed and fabricated in 0.25-μm CMOS technology and the die size is 8×8 mm² including eighty-kilobyte internal memories.

Keywords

CMOS digital integrated circuits; multi-threading; multiprocessing systems; programmable circuits; reconfigurable architectures; reduced instruction set computing; system-on-chip; 0.25 micron; 2.5 V; 250 MHz; 32 bit; 8 mm; 80 kByte; CMOS; I/O protocols; IO processors; RISC processor; SoC; context switching; data-intensive applications; internal memories; multiple IO processors; multithreaded processor; reconfigurability; single-chip programmable processor array; system-level programmable chips; CMOS technology; Clocks; Hardware; Logic devices; Microprocessors; Protocols; Prototypes; Reconfigurable logic; Reduced instruction set computing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358891

Filename

1358891