A baseband processor for pulsed ultra-wideband signals

Author

Blazquez, Raul ; Newaskar, Puneet P. ; Lee, Fred S. ; Chandrakasan, Anantha P.

Author_Institution

Microsystems Technol. Lab., MIT, Cambridge, MA, USA

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

587

Lastpage

590

Abstract

This paper presents a baseband processor for pulsed ultrawideband signals. It consists of an analog to digital converter (ADC), a clock generation system and a digital back-end. The FLASH interleaved ADC provides four bit samples at 1.2 GSPS. The back-end uses parallelization to process these samples and to reduce the signal acquisition time to 70 μs. The baseband processor was implemented in the same 0.18 μm CMOS chip as a part of a complete transceiver. A complete 193 kbps wireless link is demonstrated.

Keywords

CMOS integrated circuits; analogue-digital conversion; correlation methods; digital signal processing chips; parallel architectures; radio links; radio receivers; transceivers; 0.18 micron; 193 kbit/s; 70 mus; CMOS transceiver; FLASH interleaved ADC; UWB radio communication; UWB system-on-a-chip transceiver; baseband processor; clock generation system; correlation receiver; digital back-end parallelization; pulsed UWB signal receiver; pulsed ultra-wideband signals; signal acquisition time; wireless link; Analog-digital conversion; Bandwidth; Baseband; Clocks; Frequency synchronization; Phase locked loops; Signal processing; Signal resolution; Transceivers; Ultra wideband technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358892

Filename

1358892