Title :
The 1.44F2 memory cell technology with the stacked-surrounding gate transistor (S-SGT) DRAM
Author :
Endoh, T. ; Sakuraba, H. ; Shinmei, K. ; Masuoka, F.
Author_Institution :
Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan
Abstract :
The proposed Stacked-Surrounding Gate Transistor (S-SGT) DRAM is structured by stacking several SGT-type cells in series vertically. When the S-SGT DRAM is stacking 4 cells and one bit-line of both S-SGT and the normal DRAM has 1 K-bit cells, the S-SGT DRAM can realize a cell area per bit of 1.44F2, while cell area per bit of the normal DRAM with the same design rule is 12F2. Also the S-SGT DRAM achieves a 230% larger signal capacitance over total bit-line capacitance (Cs/Cb) than that of the normal DRAM
Keywords :
CMOS memory circuits; DRAM chips; capacitance; S-SGT DRAM; dynamic RAM; memory cell technology; stacked SGT-type cells; stacked-surrounding gate transistor DRAM; vertically-stacked cells; Capacitance; Capacitors; Equivalent circuits; Random access memory; Signal restoration; Silicon compounds; Stacking;
Conference_Titel :
Microelectronics, 2000. Proceedings. 2000 22nd International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-5235-1
DOI :
10.1109/ICMEL.2000.838730
