Detailed modeling of source/drain parasitics and their impact on MOSFETs scaling

Author

Kim, Seong-Dong ; Woo, Jason C S

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

fYear

2002

fDate

2-3 Dec. 2002

Firstpage

1

Lastpage

4

Abstract

The resistance components and key device/process parameters contributing of source/drain (S/D) parasitic resistance are investigated through advanced modeling for 50 nm gate-length MOSFET design and scaling. The silicide-diffusion contact resistance component is expected to be a major component in highly scaled nanometer MOS transistors. The key factors impact on MOSFET scaling are quantitatively examined based on 53 nm gate-length technology and the strategies for S/D engineering surmounting the scaling barriers associated with S/D parasitics are discussed.

Keywords

MOSFET; Schottky barriers; contact resistance; diffusion; semiconductor device models; 50 nm; 53 nm; MOSFET scaling; gate length; scaled nanometer MOS transistors; scaling barriers; silicide diffusion contact resistance component; source/drain parasitic resistance; CMOS technology; Contact resistance; Doping profiles; Electric resistance; MOS devices; MOSFETs; Semiconductor device modeling; Semiconductor process modeling; Silicides; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Junction Technology, 2002. IWJT. Extended Abstracts of the Third International Workshop on

Conference_Location

Tokyo, Japan

Print_ISBN

4-89114-028-3

Type

conf

DOI

10.1109/IWJT.2002.1225186

Filename

1225186