DocumentCode
1951145
Title
Design of irregular LDPC Codes for flexible Encoder and Decoder Hardware Realization
Author
Kienle, Frank ; Brack, Torben ; Wehn, Norbert
Author_Institution
Microelectron. Syst. Design Res. Group, Kaiserslautern Univ.
fYear
2006
fDate
Sept. 29 2006-Oct. 1 2006
Firstpage
296
Lastpage
300
Abstract
Low-density parity-check (LDPC) codes are among the best channel codes known today and are in discussion for current and future communications standards. LDPC codes can be efficiently modeled by Tanner-graphs. In this paper, we present a novel hardware-efficient 2-vector design method of such graphs. We show communications performance results for an exemplary code created by this approach and corresponding implementation results for a flexible, multi-rate 2V-LDPC decoder and encoder applicable for hybrid-ARQ
Keywords
decoding; graph theory; parity check codes; LDPC codes; Tanner-graphs; decoder hardware realization; flexible encoder; hardware-efficient two-vector design method; low-density parity-check codes; multirate 2V-LDPC decoder; Algorithm design and analysis; Bipartite graph; Communication standards; Design methodology; Hardware; Iterative algorithms; Iterative decoding; Microelectronics; Parity check codes; Turbo codes;
fLanguage
English
Publisher
ieee
Conference_Titel
Software in Telecommunications and Computer Networks, 2006. SoftCOM 2006. International Conference on
Conference_Location
Split
Print_ISBN
953-6114-87-9
Electronic_ISBN
953-6114-87-9
Type
conf
DOI
10.1109/SOFTCOM.2006.329769
Filename
4129923
Link To Document