Design Exploration for FPGA-Based Multiprocessor Architecture: JPEG Encoding Case Study

Author

Wu, Jason ; Williams, John ; Bergmann, Neil ; Sutton, Peter

Author_Institution

Sch. of Inf. Technol. & Electr. Eng., Univ. of Queensland, Brisbane, QLD, Australia

fYear

2009

fDate

5-7 April 2009

Firstpage

299

Lastpage

302

Abstract

This paper presents a system level design flow which enables rapid design space exploration and a verification tool to assist a designer to identify an FPGA-based MPSoC for stream-oriented application. The case study, JPEG encoding, illustrates how the tool exploits the task-level parallelism and produces a suitable architectural design, binding and scheduling algorithm while satisfying physical constraints.

Keywords

field programmable gate arrays; formal verification; image coding; logic design; parallel architectures; processor scheduling; system-on-chip; FPGA-based multiprocessor architecture; JPEG encoding case study; MPSoC; rapid design space exploration; scheduling algorithm; stream-oriented application; system level design flow; task-level parallelism; verification tool; Application software; Australia; Computer architecture; Data processing; Encoding; Field programmable gate arrays; Hardware; Information technology; Resource management; Space exploration; FPGA; JPEG; MPSoC;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Custom Computing Machines, 2009. FCCM '09. 17th IEEE Symposium on

Conference_Location

Napa, CA

Print_ISBN

978-0-7695-3716-0

Type

conf

DOI

10.1109/FCCM.2009.7

Filename

5290893