Gate insulating layer impact on the extension profile of the sub-50 nm p-MOSFET

The gate insulating layer impact on the extension profiles of the sub-50 nm p-MOSFETs is evaluated by direct visualization with the use of STM. The variation in the overlap between the gate electrode and the extension is measured. This variation is qualitatively consistent with that expected from the roll-off characteristics. Based on the results, it is considered that the horizontal extension profile strongly depends on the stress near the Si/SiON interface. It is also indicated that the insulating layer strongly affects on the horizontal abruptness of the junction near the Si/SiON interface.