DocumentCode
1951262
Title
A low power 0.25 mu m CMOS technology
Author
Woerlee, P.H. ; Juffermans, C.A.H. ; Lifka, H. ; Manders, W. ; Pomp, H. ; Paulzen, G. ; Walker, A.J. ; Woltjer, R.
Author_Institution
Philips Res. Lab., Eindhoven, Netherlands
fYear
1992
fDate
13-16 Dec. 1992
Firstpage
31
Lastpage
34
Abstract
A 0.25 mu m CMOS technology with scaled LOCOS isolation, twin implanted well, 7.5 nm gate oxide thickness, surface channel NMOS and PMOS devices, shallow n- and p-junctions and thin TiSi/sub 2/ salicide is described. The technology is optimized for a reduced supply voltage of 2.5 V. The device design and fabrication, device characterisation and inverter delay are presented.<>
Keywords
CMOS integrated circuits; integrated circuit technology; ion implantation; logic gates; 0.25 micron; 2.5 V; CMOS technology; TiSi/sub 2/ salicide; device characterisation; device design; gate oxide thickness; inverter delay; reduced supply voltage; scaled LOCOS isolation; shallow n-junctions; shallow p-junctions; surface channel NMOS devices; surface channel PMOS devices; twin implanted well; CMOS integrated circuits; Integrated circuit fabrication; Ion implantation;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-0817-4
Type
conf
DOI
10.1109/IEDM.1992.307302
Filename
307302
Link To Document