Elevated source/drain engineering with smooth surface morphology for ultrathin-SOI CMOS

A novel selective epitaxial growth (SEG) technology which combines low-temperature UHV-CVD and low-damage sidewall etch-back with a Cl/sub 2/-plasma is experimentally demonstrated for elevated S/D ultra-thin SOI CMOS devices. It is found that the deviation of the parasitic S/D series resistance in elevated S/D sub-40-nm-thick SOI FETs can be nearly as low as that in bulk FETs because the excellent epi-Si surface morphology enables a uniform CoSi/sub 2/ film. Moreover, neither gate/drain bridging nor any other leakage phenomena are pronounced. These results mean that this SEG technology is promising for elevated S/D ultra-thin SOI CMOS devices for the 90-nm technology node and beyond.