FPGA Floating Point Datapath Compiler

This paper will describe the architecture of a compiler which will convert an untimed C description of a floating point expression into a synthesizable datapath optimized for FPGAs. The concept of floating point fused datapath synthesis will be reviewed, along with the expected functional efficiency gains. The dataflow graph structure used by the compiler will be detailed, followed by the description of the restructuring and optimizations, as well as the required data integrity considerations. In particular, datapath architecture considerations for improved FPGA fitting will be explored. Application examples for a matrix calculations will be used to illustrate the improvements of the compiled datapath compared to the traditional core based approach, and the mechanisms behind them.