New VLSI design of a max-log-MAP decoder

Author

Sabeti, Leila ; Ahmadi, Majid ; Tepe, Kemal

Author_Institution

Res. Centre for Intergarated Microsyst., Windsor Univ., Ont., Canada

fYear

2004

fDate

20-23 June 2004

Firstpage

37

Lastpage

40

Abstract

This paper proposes a new design of a MAP decoder suitable for ASIC. The decoder architecture is parallel and pipeline, which makes the design applicable to bit rate communication systems. Max-log-MAP algorithm, which offers a good compromise between performance and complexity, is selected for implementation. One of the components of this algorithm, namely, the transition probability (γ) calculation unit is studied and a new low complexity design of this unit is proposed. Overall decoder design is flexible to the transmission block lengths, which makes it suitable for variable length transmission systems.

Keywords

VLSI; application specific integrated circuits; maximum likelihood decoding; parallel architectures; pipeline processing; probability; ASIC; VLSI design; bit rate communication system; decoder architecture; max-log MAP algorithm; max-log MAP decoder; parallel architecture; pipeline architecture; transition probability; variable length transmission system; Algorithm design and analysis; Application specific integrated circuits; Communication channels; Forward error correction; Iterative algorithms; Iterative decoding; Pipelines; Probability; Turbo codes; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on

Print_ISBN

0-7803-8322-2

Type

conf

DOI

10.1109/NEWCAS.2004.1359009

Filename

1359009