Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems

This paper analyzes fragmentation issues and proves that the reconfigurable area must be tiled much finer as has been done in existing approaches. The optimal tile grid can typically only be implemented by tiling the reconfigurable area into a two-dimensional grid. This will further increase the utilization of dedicated resources such as block RAMs. In order to provide communication with the reconfigurable modules, the novel ReCoBus communication architecture is enhanced for two-dimensional communication. A case study will demonstrate a system with 248 individual logic tiles that are each less than 200 LUTs in size while still being able of providing a module connection in each particular tile.