Image compression using coarse grain parallel processing

The architecture and application of a multiprocessor system based on a homogeneous array of DSP processors are discussed. The system consists of floating point digital signal processors connected to each other via fast serial links. Each processor has access to a globally shared memory, and a multiple bus architecture in combination with a dual ported memory allows communication with a host controller. The architecture has been implemented and applied to the prototyping of video compression algorithms. The algorithms implemented include JPEG still-frame compression, CCITT H.261, and MPEG coding. These techniques may be decomposed into variable length encode or decode portions in tandem with a compute intensive element. This decomposition and its mapping into parallel processors is described