The arithmetic cube II: a second generation VLSI DSP processor

Author

Irwin, Mary Jane ; Owens, Robert M. ; Kelliher, Thomas P. ; Leung, Kin-Ki ; Vishwanath, Mohan

Author_Institution

Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA

fYear

1991

fDate

14-17 Apr 1991

Firstpage

1125

Abstract

A description is given of the synthesis, design, and simulation of the arithmetic cube II, a second-generation, high-performance digital signal processing architecture. The architecture implements the so-called small-n algorithms. The authors are currently building a CMOS prototype system which should be capable of computing a 1024 point complex DFT in 410 μs

Keywords

CMOS integrated circuits; VLSI; digital signal processing chips; fast Fourier transforms; CMOS; DSP; VLSI; arithmetic cube II; complex DFT; design; digital signal processing architecture; simulation; small-n algorithms; synthesis; Buildings; Computational modeling; Computer architecture; Digital arithmetic; Digital signal processing; Prototypes; Signal design; Signal processing algorithms; Signal synthesis; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on

Conference_Location

Toronto, Ont.

ISSN

1520-6149

Print_ISBN

0-7803-0003-3

Type

conf

DOI

10.1109/ICASSP.1991.150564

Filename

150564

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1951869