More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control

In this paper we exploit FPGA flexibility in the context of accelerating the solution of many small systems of linear equations, a problem central to model predictive control (MPC). The main observation exploited by this work is the distinction between accuracy (meaning the degree of correctness of a final computational result) and precision (meaning the degree of correctness of each atomic computation). Using iterative methods for solving linear systems, one can obtain improved accuracy either by running more iterations or by using more precise internal computations, unlike direct methods, where accuracy is only a function of operation precision. Thus, in iterative methods, for a given accuracy requirement we may conduct fewer iterations in a higher precision, or more in a lower precision. We argue that this suits FPGA architectures ideally, as low precision operations result in greater parallelism for any fixed area constraint. We show that we may therefore optimize the performance by balancing iteration count and operation precision, resulting in a several-fold speed improvement over a double-precision implementation, but with the same final result accuracy. Exploring this trade-off it is possible to provide a speed-up of 26x on average, 14x in the worst case and 36x in the best, compared to a high-end CPU running at 3.0 GHz. This has the potential to allow modern high-performance control techniques to be used in novel settings such as aircraft and diesel engines. Is the distinction between accuracy (meaning the degree of correctness of a final computational result) and precision(meaning the degree of correctness of each atomic computation). Using iterative methods for solving linear systems,one can obtain improved accuracy either by running more iterations or by using more precise internal computations, unlike direct methods, where accuracy is only a function of operation precision. Thus, in iterative methods, for a given accuracy requirement we may conduct fewe- r iterations in a higher precision, or more in a lower precision. We argue that this suits FPGA architectures ideally, as low precision operations result in greater parallelism for any fixed area constraint. We show that we may therefore optimize the performance by balancing iteration count and operation precision,resulting in a several-fold speed improvement over a double-precision implementation, but with the same final result accuracy. Exploring this trade-off it is possible to provide a speed-up of 26times on average, 14times in the worst case and 36times in the best, compared to a high-end CPU running at 3.0 GHz. This has the potential to allow modern high-performance control techniques to be used in novel settings such as aircraft and diesel engines.