Title :
3-D topography simulation of via holes using generalized solid modeling
Author :
Tazawa, S. ; Leon, F.A. ; Anderson, G.D. ; Abe, T. ; Saito, K. ; Yoshii, A. ; Scharfetter, D.L.
Author_Institution :
NTT LSI Labs., Kanagawa, Japan
Abstract :
A 3-D deposition and etching simulator using "generalized solid modeling (GSM) method" has been developed. This simulator uses the boundary representation model to define solids, forming the individual materials of the wafer. Then, basic solid modeling operations are used to deform the solids without the need for complex loop removal algorithms. In this simulator, the "3-D unified equation," whose parameters are the same as those of the 2-D equation, is used to calculate a local deposition and/or etching rate. To precisely calculate the movement vector of each vertex for complex 3-D structures, the "3-D plane model" and "semi-sphere mesh method" have been developed. This simulator has been applied to the patterning and metallization of via holes, and its results closely agree with experimental results.<>
Keywords :
digital simulation; mesh generation; metallisation; semiconductor process modelling; solid modelling; sputter deposition; sputter etching; 3D plane model; 3D topography simulation; 3D unified equation; boundary representation model; deposition simulator; etching simulator; generalized solid modeling; metallization; semi-sphere mesh method; submicron interconnect; via holes; Geometric modeling; Mesh generation; Metallization; Semiconductor process modeling; Simulation; Sputter etching; Sputtering;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307335