On-chip signaling for ultra low-voltage 0.13 μm CMOS SOI technology

This paper presents a current-mode signaling technique in an ultra low-voltage environment. At power supply voltage V_DD below 500 mV, the CMOS gate delay is dominant with regard to the delay in the interconnect. Thus, buffering techniques using inverter chains are not efficient, especially for high data rates. In this paper, we reevaluate the benefits of current sensing for ULV applications and present a new auto-regulated current sensing scheme (ARCS), which allows power savings of more than 55% on a 2 pF interconnect for high data rate signals at almost no performance penalty, comparing to voltage mode signaling. The ARCS scheme has been implemented in a 130 nm partially depleted SOI technology.