Thermal modeling of active embedded chip into high density electronic board

The recent PWB embedding technology is an attractive packaging alternative that allows a very high degree of miniaturization by stacking multiple core layers of embedded chips, using copper filled micro-vias as interconnections to improve electrical performances. The adoption of disruptive technology in future PWB designs will further increase the thermal management challenges by concentrating heat dissipation at the heart of the organic substrate and exacerbate the need of adequate cooling. In order to allow the electronic designer to early analyse the limits of the power dissipation, depending on the embedded chip location inside the board, as well as the chip thermal interactions with other chips or SMD components, an analytic thermal modelling approach has been established. The presented work describes the comparison of the analytic model results with the numerical detailed models of various embedded chips, and debates about the need or not to simulate in full details the embedded chips as well as the surrounding layers and micro-via structures of the substrate. The thermal behaviour predictions of the analytic model, found to be within ±10% of relative error, demonstrate its relevance to model an embedded chip and its neighbouring heating chips or components. The proposed approach promotes a new practical solution to achieve a more efficient design and to early identify the potential issues of board cooling.