Using partial reconfiguration and high-level models to accelerate FPGA design validation

Design validation is the most time-consuming task in the FPGA design cycle. Although manufacturers and third-party vendors offer a range of tools that provide different perspectives of a design, many require that the design be fully re-implemented for parameter modifications or do not allow the design to be run at full-speed. Designs are frequently first modeled using a high-level language then later rewritten in a hardware description language, first for simulation and then later modified for synthesis. IP and third-party cores may differ during these final two stages complicating development and validation. Our approach provides a means of directly validating synthesized hardware designs with the original high-level model, abstracting away the traditional bit-level view of designs. The Dynamic Modular Development (DMD) framework accelerates module turnaround by reusing floorplans and placing frequently changing modules into separate, partially reconfigurable regions. The debug framework also leverages these reconfigurable regions to accelerate the modification of dynamic, software-like breakpoints for low-level analysis.