PSO-based charge pump chip area minimization

Author

Alicalapa, Frederic ; Luk, Jean Daniel Lan Sun ; Aloulou, Rahma ; Mnif, Hassene ; Loulou, Mourad

Author_Institution

LE2P Lab., Univ. of La Reunion, St. Denis, France

fYear

2012

fDate

19-21 Sept. 2012

Firstpage

133

Lastpage

136

Abstract

In this paper a solution of the well-known silicon area/performance dilemma and an energy harvesting circuit for wireless sensor nodes are presented. A PSO-based integrated circuit area optimization methodology is proposed. The study is performed on a charge pump circuit, using a 0.35μm Si-CMOS process. The PSO sizing strategy has been implemented using a Spice kernel and Matlab environment. The chip size has been reduced from 583μm² to 179μm² after the optimization process. Simulation results from the 0.35μm parameters are given. When driving a capacitive load of 50pF, the output-generated voltage is 4V from a 1.3V input voltage. The simulated pumping gain is 3.1.

Keywords

SPICE; capacitance; charge pump circuits; circuit optimisation; elemental semiconductors; energy harvesting; minimisation; particle swarm optimisation; silicon; Matlab environment; PSO sizing strategy; PSO-based charge pump chip area minimization; PSO-based integrated circuit area optimization methodology; Si; Spice kernel; capacitive load; charge pump circuit; energy harvesting circuit; gain 3.1 dB; output-generated voltage; particle swarm optimization; silicon area/performance dilemma; size 0.35 mum; voltage 1.3 V; voltage 4 V; wireless sensor node; Capacitors; Charge pumps; Clocks; Integrated circuit modeling; Optimization; Threshold voltage; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on

Conference_Location

Seville

Print_ISBN

978-1-4673-0685-0

Type

conf

DOI

10.1109/SMACD.2012.6339435

Filename

6339435